This is just a nitpicking question. Do Intel chips still have some space/transistors dedicated to SSE3? If they do, why can’t they implement SSE3 by other, more powerful instrutions (like AVX) to save die space?
This is just a nitpicking question. Do Intel chips still have some space/transistors dedicated to SSE3? If they do, why can’t they implement SSE3 by other, more powerful instrutions (like AVX) to save die space?
No, no CPU has seperate FPUs for SSE & AVX - it’s compiled to the same set of uOps by microcode.
Recent x86 CPUs go as far as implementing x87 in the 128b FPU too.
That’s not how it works, only a few overtly complex instructions are implemented in microcode and they are slow, most instructions use a random logic decoder.
in x86 that’s not the case, only the critical path x86 instructions are implemented directly in logic lookup tables in the decoder. Some of the less used ones are on the uCode ROM on chip. And a bunch more on PAL code on off-chip ROM. And a few of the rarest ones are on the exception manager libraries of the OS.
A big chunk of the x86 ISA is rarely used so this tiered implementation has been used at least since Nehalem if not before.