That needs a very big die.very big for cutrent mobo platforms. But I can see it being tried.making big dies and putting cache to outer borders of CPU walls. And no vchace is vertical cache it son top of die cover and chip itself. Not around it
Cache surrounding the die is probably better than stacking it on top of the die anyway. Would solve a good few of the current limitations of the X3D CPUs.
that breaks the purpose of a cache, you want a cache to reduce service times, larger caches take longer to process, it’s diminishing results after a point, they also take A LOT MORE area on the die
I waiting for us to get GB amounts of cache on consumer chips like is starting to show up in enterprise/server chips.
That will be useful.
That needs a very big die.very big for cutrent mobo platforms. But I can see it being tried.making big dies and putting cache to outer borders of CPU walls. And no vchace is vertical cache it son top of die cover and chip itself. Not around it
Cache surrounding the die is probably better than stacking it on top of the die anyway. Would solve a good few of the current limitations of the X3D CPUs.
that breaks the purpose of a cache, you want a cache to reduce service times, larger caches take longer to process, it’s diminishing results after a point, they also take A LOT MORE area on the die