Your calculations are off. No one expects to have constant time to double the address size, certainly for physical RAM – what is approximately true (but slowing down) is constant time to need each additional bit of physical address space:

• 1974 8080, 16 bits

• 1978 8086, 20 bits, 1.0 years/bit

• 1985 80386, 32 bits, 0.6 years/bit

• 1995 Pentium Pro, 40 bits, 1.25 years/bit

• 2003 Athlon64, 40 bits, n/a

• 2006 Core 2, 36 bits, n/a (going backwards!)

• 2014 Haswell-E [1], 46 bits, 1.9 years/bit (since Pentium Pro)

• 2019 Ice Lake, 52 bits, 0.8 years/bit

The overall average is 36 extra address bits in 45 years or 1.25 years/bit.

At this rate, we’re going to need more than 64 physical address bits around 2035. The need for more than 64 virtual address bits is probably about 5 years earlier, in 2030.

You could make similar lists of virtual address space on the one hand, or actual maximum RAM supported on the other hand. Those would give different rates, but I think the trend would be the same.

[1] not 100% sure this was the first

The headline is of course confused. The 64 core chips (SG2042, SG2044) use Chinese-developed THead cores. Only the 16 core chip (SG2380) is using SiFive cores.

RISC-V extensions have compatibility issues, and the company had to develop a new chip to accommodate the final vector extensions, Liuxi told HPCwire.

Liuxi should be more accurate. RVV 0.7 is a draft version with absolutely zero expectation that it will be compatible with the 1.0 version. Freedom to make radical and incompatible changes from draft to draft is the whole point of having draft versions.