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Joined 1 year ago
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Cake day: October 25th, 2023

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  • …but if you think AMD hasn’t gone to all this trouble to break away from monolithic designs with MCDs and GCDs, and not iterate with a multi GCD design…then I dunno what to tell you bro…🤷

    It’s not as impressive as you make it out to be. Splitting the MCDs and GCDs is certainly pretty nice, but both Intel and AMD have shown to have better and more advanced packaging capabilities in their GPUs- with MI300 and PVC- the only reason they haven’t come to consumers yet is cost and complexity chiefly.

    However, if AMD using something MI300esque with RDNA 4… and failed, then yes, it stands to reason that only the monolithic skus would remain.

    Alternatively, the base RDNA 4 arch could just be so cooked they thought it wasn’t worth the effort of developing the more expensive and complicated chiplet skus.

    Or who knows, maybe it’s a combination of the two, or something else.

    Also, the idea that AMD has N44/N48 and can just glue the two together to act as their flagship is also wrong. There has to be additional interconnect logic among other things added to the two dies. If the chiplet dies are canned, then they have to do expensive and time consuming respins on their existing planned RDNA 4 dies (N44/48) in order for them to be allowed to be used in chiplet designs.







  • when MTL has a 128MB cache on SOC die.

    It doesn’t tho

    And the renders for the on package memory have the two memory chips separate from the die with no safe area on the package border, when Intel would traditionally try to have them right next to each other.

    Idk, it looks very similar to this

    And why use N3 when Intel will have Backside power with their 3nm node?

    Bcuz they are lame lol.

    Intel talked about using TSMC N3 nodes in their products before. It won’t be too surprising to see it in client CPU tiles as well.








  • Also I’d like to know whether AMD’s approach to hybrid architectures (zen4 + zen4c) is a better or worse approach than having multiple core architectures with differing IPC and ISA capabilities.

    Different trade offs, no clear answer.

    And given that raptor lake consumes more power at peak power consumption than zen4, is it even worth it to have P+E cores?

    Yes.

    Would intel have attained higher multithreaded performance if it offered 10 or 12 p cores + Avx512 rather than using gracemont?

    No.

    Like what’s the point of gracemont if overall raptor lake power consumption is much higher vs older Intel CPUs ??

    It’s not, at least iso perf.


  • overpriced

    Ye, flagship CPUs are always over priced

    marketing chip

    How? Intel is the one with the mindshare with non-tech inclined people. The amount of mindshare they have for their poor record over the past couple years in client is really impressive.

    which cripples itself under gaming

    3D cache with Zen 4 is just way more impressive than the bloated, power hungry RPC core. And more performant to boot.

    while running hotter at a lower power draw…

    No one cares about that lmao

    Also sorry you had to get a 3435x. That mesh must suck lol




  • Kinda.

    Though I will add, what Intel calls “10nm” is equivalent to TSMC’s “7nm”.

    So yes, if they fail to progress past Intel 7, they will be screwed in the future. Overcoming an entire nodes difference in PPA is extremely hard, and with Intel having worse design teams than its competitors, it becomes an esentially impossible task.

    Intel does have Intel 4, and they claim they are shipping it to OEMs already, with MTL (the Intel 4 product) launching in Dec. However it appears it’s mobile only, and we have no idea about the volume. If it’s just a paper launch, and yields/volumes take years to fix, (like Intel’s 10nm), then yes, they will be hurt badly.

    Idk if I would go as far to say they would be screwed, but the company they would be in this scenario would be unrecognizable compared to the current Intel.