Isn’t this an obvious fake by someone who doesn’t even know what MTL is set up like?
Eg: they have an 8MB L4 cache on the CPU die for LNL when MTL has a 128MB cache on SOC die.
And the renders for the on package memory have the two memory chips separate from the die with no safe area on the package border, when Intel would traditionally try to have them right next to each other.
And why use N3 when Intel will have Backside power with their 3nm node?
And the renders for the on package memory have the two memory chips separate from the die with no safe area on the package border, when Intel would traditionally try to have them right next to each other.
nice comment fuss with digital warrior btw!
It was quite frustrating yet fun to see a regular user trying to defend his ill-informed contrarian position against someone who clearly has industry info.
btw I know that 90% of what he said are correct. 90% because the rest is kinda up to interpretation.
FWIW, if this is a fake, someone put an enormous amount of work into irrelevant things e.g. mechanical dimensions.
Eg: they have an 8MB L4 cache on the CPU die for LNL when MTL has a 128MB cache on SOC die.
The 8 MB is not an L4 cache since it is in parallel with the last level cache rather than above it in the hierarchy. This detail actually looks credible since it is a logical progression from MTL where the GPU memory access was also split off from the LLC. Now they’re splitting off the rest.
Isn’t this an obvious fake by someone who doesn’t even know what MTL is set up like?
Eg: they have an 8MB L4 cache on the CPU die for LNL when MTL has a 128MB cache on SOC die.
And the renders for the on package memory have the two memory chips separate from the die with no safe area on the package border, when Intel would traditionally try to have them right next to each other.
And why use N3 when Intel will have Backside power with their 3nm node?
It doesn’t tho
Idk, it looks very similar to this
Bcuz they are lame lol.
Intel talked about using TSMC N3 nodes in their products before. It won’t be too surprising to see it in client CPU tiles as well.
https://www.tomshardware.com/news/intel-patent-reveals-meteor-lake-adamantine-l4-cache
https://www.phoronix.com/news/Linux-Patch-Intel-MTL-L4-Cache
nice comment fuss with digital warrior btw!
It was quite frustrating yet fun to see a regular user trying to defend his ill-informed contrarian position against someone who clearly has industry info.
btw I know that 90% of what he said are correct. 90% because the rest is kinda up to interpretation.
FWIW, if this is a fake, someone put an enormous amount of work into irrelevant things e.g. mechanical dimensions.
The 8 MB is not an L4 cache since it is in parallel with the last level cache rather than above it in the hierarchy. This detail actually looks credible since it is a logical progression from MTL where the GPU memory access was also split off from the LLC. Now they’re splitting off the rest.
Probably limited capacity and priorities