Milling a slot out of a piece of aluminum is not that difficult. It also has a lot lower chance of fucking up a perfectly good notebook part.

Xenon’s critical point is nearly at room temperature, so I guess it’s not impossible for Xe-LPG to exist in a computer.

The reason for the shrinking memory buses is the bad scaling of IO with newer processes. The memory controllers on AD102 have basically the same footprint as that on GA102, in spite of there being a gigantic increase in overall transistor density

Ethereum mining hasn’t been a thing for a year now btw

You would think so, but there are some really bad SoCs out there, using only Arm A5x series cores that have no business rendering a website and will give you an authentic early 2010s mobile web browsing experience.

That’s only true for intel, who disable part of the L3 along with the cores. AMD however has the full L3 enabled on their 6-cores.

The marketing folks love to add up the L2 cache as well, but since that is not shared cache, each core still has the exact same amount of cache available to it, in spite of having a lower number on the spec sheet.

GDDR5 used in the Xbox One is DDR memory. It just means Double Data Rate.

GDDR6 used in the Series X however isn’t. It’s technically Quad Data Rate, but they decided to keep the naming scheme.

I would love to plug headphones into my phone, but I hate 3.5 mm. It’s like mini-USB in the way that it will easily break the plug or the socket when you accidentally rip it out. Or even worse, it can pull devices out of pockets or off desks, because it’s not designed to pull out when sideways forces are applied.

That’s something that Apple’s lightning connector, USB C and USB Micro are specifically designed around. Any significant force in any direction will slip out the plug without damaging either end.

The x86 instructions go through a translation layer that turns them into CPU specific instructions (microcode). So the CPU doesn’t need any specific hardware to be compatible with these old instructions, it just needs to know how to get the same result with microcode.

The x86 instructions go through a translation layer that turns them into CPU specific instructions (microcode). So the CPU doesn’t need any specific hardware to be compatible with these old instructions, it just needs to know how to get the same result with microcode.

Giving individual cores the ability to boost as high as possible means that in scenarios where multi-threading doesn’t scale perfectly, you can still squeeze as much as possible out of the other cores. Because the thread that bottlenecks the most can be run as fast as possible.

Or in other words: Limiting the top boost clock by 5% will effectively slow the entire CPU down by 5% as well.

That’s why if you want to limit the CPU power draw, you should do it either via the power limit, or by reducing the throttling threshold. The latter can give you better performance in “race to finish” situations, where you only need a short power boost to finish a task, but it’s less consistent.

Honestly I think it should become a lot better in 5 to 10 years, since a lot of their problems seem to come from being understaffed. Keep in mind, they were a fairly small company on the verge of bankruptcy just a few years ago, and you can only onboard so many people each year without causing inefficiency.

So their competence in software as well as hardware should be improving, not getting worse.