AMD’s chiplet strategy in laptops: balancing innovation and power efficiency. AMD says that chiplet design for mainstream mobile APUs is challenging due to power constraints. The chiplet approach has been instrumental in the success of the Ryzen CPU series. In the domain of laptops, AMD is still evaluating how to approach this idea. During a […]
I always wondered if their MCDs used on RDNA3 could interface with DDR5 memory.
I know there were gt 1030 cards that used ddr4 memory I think Intel released their first discrete GPU before Arc that used ddr4 as well I thought.
Each MCD is 2x32 bit total. Could you pair 1 or 2 with an APU graphics and CPU die I wonder? The cache certainly would alleviate the bandwidth struggles keeping the graphics capabilities limited on APUs.