- cross-posted to:
- amd
- cross-posted to:
- amd
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Why is this news? Seriously, the entire point is that they’re CONSIDERING switching to chiplet APU’s once it becomes realistic. Like, no shit Sherlock.
Signed, Captain Obvious
They’re saying that 3D cache APUs aren’t coming soon because of costs. Why do you have all your feathers ruffled over some news? Lol
Not quality hardware discussion
The implementation of APU chiplets indirectly affects the fabrication and timeline of 3D vcache containing APU’s, in the question of affordability. Though it might not be an obvious link or conclusion, evidently…
This has nothing to do with 3D cache.
Yes the chip size needs to be larger for it to be profitable. Look at Apple … same philosophy.
Well technically we’re going to meet mainstream 1nm transistors the laws of physics will allow fairly soon so better not start counting your chicks before your eggs so soon AMD.
They should put one or two Zen c core on the io die no? That way they can completely power down core chiplets when doing light work. Since the igpu is also on io die, there will be massive efficiency gains when watching videos, listening to music, etc.
you can overcome the extra power draw (mostly) but it costs a lot in fancy packaging. Doing stuff like ahving a silicon interposer layer bridging the chips rater than talking through the organic substrate.
Yeah it’s basically widely known now that chiplet Ryzens have noticeably higher idle power draw than either monolithic Ryzens or monolithic Intel chips. I am curious how Meteor Lake’s chiplets are going to avoid the idle power penalty.
The interposer means a less power is used per bit moved between tiles compared to the substrate AMD uses, and the CPU and GPU tile can be shut down when not needed. This leaves the SoC tile’s 2 LPe-cores and the memory controllers, I/O, and display drivers active so the system can idle without the power-hungry parts of the chip doing anything. Current monolithic Ryzen and Core i can’t power down to that extent. Video playback for example, can take place on the LPe-cores, so expect long battery life in that scenario.
Current monolithic Ryzen and Core i can’t power down to that extent.
Why not? I get that the LP-e cores are optimized for lower voltage/frequency than generalist cores historically have been, but monolithic chips can use power gating and multiple voltage domains too.
Video playback for example, can take place on the LPe-cores, so expect long battery life in that scenario.
But what about video playback in a web browser? With 30+ background tabs?
If Meteor Lake manages to avoid regressing real-world battery life, I will be pleasantly surprised.
On current CPUs, anything that needs CPU attention has to wake up the big cores. Ryzen only has big cores currently (Zen4C should be equal power within the frequency both cores can reach) and 12/13th gen Thread Director goes to the P-cores first. This means that every time you need to do something, there is a brief period where some power-hungry cores have to come out of whatever low-power state they use to perform that thing.
With MTL the main CPU tile can in theory stay powered-down while the LPe-cores run code outside of them. Thread Director goes to these cores first, so only tasks that need more CPU are escalated to the main CPU cores.
That is a question I can’t answer right now. It’s a wait and see both because MTL isn’t out yet, and because there are a ton of variables that can change CPU behavior in 30 tabs. Since the memory controllers are on the SoC tile, in theory they can all stay loaded, and only switching between tas would briefly hit the main CPU tile. It is also totally possible that some of those tabs are more demanding, say they leverage some hardware acceleration features of the GPU. That would involve waking that tile during interactions with the page at least.
It’s possible power plans may affect how aggressively tiles are put to sleep, in which case you could get into OEM or even model-specific behaviors that would only be comparable through reviews.
I am curious how Meteor Lake’s chiplets are going to avoid the idle power penalty.
The lower power island, the SoC tile with 2 e-cores allows Intel to turn off silicon on the big compute chip.
Allows, but how well does the big compute chip stay off? Given the typical OS background noise and web browsers/pages that suck 37 CPUs on the way through the parking lot to process a stream of mouse events.
Somewhat, but it seems like less then before. I did a quick poll of a few people using the current Gen chips, and it seemed pretty similar between the 13600k and 7800x3d
7000 series uses a new I/O die on TSMC 6nm instead of GloFo 14nm, that’s probably making a big difference
Meteor lake uses a more expensive, lower yield but higher performance and efficiency approach to MCM than Ryzen desktop CPUs. However Ryzen uses their approach precisely for the yields and cost
At full blast, efficiency is lost, but at low power state, the CPU can shut down most of the tiles to actually gain net efficiency
They seem to have fixed it for some people with RDNA3. They claimed it was specifically optimizations that are sometimes monitor specific, but I and many people, always assumed it was because of chiplets.
I’ll be curious how RDNA4 will turn out, and if it’s chiplets or not. Bad power draw in laptops, is probably one reason we hardly see any RDNA3 laptops.
The 7900M being up to 200W is wild to me. Even the 7700S is higher power than my 6800S. I don’t know what happened in RDNA3’s development, but it feels like a testbed generation where ideas are good, but something went awry getting them into the physical world.